1. Field of the Invention
The present invention relates to an apparatus and a computer implemented method for selecting test patterns and a computer product program for controlling a computer system so as to select test patterns and in particular to a fault simulation technology of a large scale integrated circuit (LSI) so as to reduce the number of test patterns effectively by using a fault coverage reflecting layout information correlating with quality of the LSI.
2. Description of the Related Art
In manufacturing tests, LSI chips are inspected to ensure that the LSI chips have no defects. The manufacturing tests employ test patterns for detecting faults that possibly occur in internal circuit of an LSI. Since a fault coverage of each of the test patterns is an important factor in such manufacturing tests, the fault coverage of each of the test patterns is previously evaluated by fault simulation.
When a logic circuit of an LSI is designed, multiple verification patterns are used to verify the function of the logic circuit. Such verification patterns for designing the logic circuit are converted to the test patterns in the manufacturing tests. However, since the chip gate count increases in accordance with enlarging degree of on-chip integration of the LSI recently, the fault simulation with all verification patterns requires tremendous CPU resources. Therefore, converting all verification patterns to the test patterns causes increased costs of the manufacturing tests and reducing the number of verification patterns converted to the test patterns is desired.
A method for reducing the number of test patterns without decreasing the fault coverage is proposed in published Japanese Patent Application P2001-273160. According to the proposed method, verification functional coverage of each verification pattern for register transfer level (RTL) description of the LSI is evaluated. Subsequently, the minimum verification patterns equivalent to all verification patterns in functional verification coverage or RTL code coverage are extracted and defined as a “selected test pattern set”. In contrast, other verification patterns are defined as an “unselected test pattern set”. Thereafter, the fault simulation generates a “first undetected fault list” including faults that are undetected by the selected test pattern set in the logic circuit. Further, a “second undetected fault list” is generated by extracting faults from the first undetected fault list by random. Thereafter, whether each of the unselected test pattern set detects the faults included in the second undetected fault list is determined and “detected fault list by the unselected test pattern” is generated. Based on the detected fault lists by the unselected test patterns, the verification patterns contributing to increase the fault coverage are extracted from the unselected test pattern set and are defined as an “additionally selected test pattern set”. In this manner, the selected test pattern set and the additionally selected test pattern set are extracted from the verification patterns and are consequently employed to test the LSI chips in the manufacturing tests.
In addition, a method for adding a weight reflecting layout information on circuit elements to each fault is proposed in published Japanese Patent Application P2000-276500. Such weight is calculated by referring to logic connection nodes and layout information of the circuit.
In the method for reducing test patterns described above, procedure for extracting the selected test pattern set based on the functional verification coverage by functional verification coverage evaluating tools and procedure for selecting the additionally selected test pattern set based on the fault coverage by fault simulating tools are connected effectively. In this manner, the total test patterns employed in the manufacturing tests are reduced without or negligibly small decrease of the fault coverage.
However, the faults based on a fault model used in this method only reflect logical definition of internal connection nodes of the logic circuit or input/output (I/O) terminals of basic cells and do not reflect information of layout of the elements, such as length of wires, length of closely placed part of wire pairs, area of basic cells, length of closely placed part of wire pairs and the number of minimum size contacts, correlating to real defects in the LSI chips. Consequently, the verification patterns failing to effectively detect the real defects may be more selected as the additional selected test patterns, which causes longer manufacturing tests time, compared with the case in which layout information is taken into account.